A Comparative Study of Vector Dot Product Implementations on Fpgas with Distributed Arithmetic and Residue Number System

Vector dot product or multiply accumulate (MAC) is a frequently used operation in digital signal processing algorithms. When implementing digital signal processors (DSPs) using field programmable gate arrays (FPGAs), significant area and speed advantages are possible if the implementation architecture has a direct mapping on the underlying structure of FPGAs. Such a synergy is present in both distributed arithmetic (DA) and residue number system (RNS) based implementations. Both these techniques use FPGA look-up tables (LUTs) for implementing ROMs for their basic processing elements. In addition, RNS helps to hide the inefficiencies of FPGAs in handling large word lengths by breaking up the computation into parallel operations on smaller residues. The fusion of DA and RNS is also possible which combines the advantages of both the techniques.